1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device.
2. Description of the Related Art
A nonvolatile memory device retains data stored therein even when the power supply to the device is turned-off. Data may be stored in a nonvolatile memory by shifting the threshold voltage of a memory cell to control the amount of electrical charges retained in the conduction band of a floating gate.
Generally, when a program pulse is applied to the floating gate, the threshold voltage of the memory cell rises. The threshold voltage of the memory cell may shift depending on the value of data to be stored in the memory cell using the program pulse. Since a plurality of memory cells of nonvolatile memory may have slightly different characteristics, the threshold voltages of memory cells storing the same data are not identical, but form a distribution.
In a nonvolatile memory, memory cells storing 1-bit data or two- or three-bit data are known. A memory cell capable of storing 1-bit data is referred to as a single level cell (SLC), whereas a memory cell capable of storing two or more bits is referred to as a multi-level cell (MLC). An SLC may have an erase state or a program state depending on a threshold voltage. An MLC has an erase state or a plurality of program states depending on a threshold voltage.
FIG. 1 is a diagram showing a distribution of threshold voltages of an MLC storing 2-bit data.
As shown in FIG. 1, the threshold voltages of memory cells may vary depending on the program states of the memory cells. Generally, the threshold voltages of memory cells in an erase state ERA are lower than a first voltage PV1. The threshold voltages of memory cells in a first program state A may be higher than or equal to the first voltage PV1 and lower than a second voltage PV2. The threshold voltages of memory cells in a second program state B may be higher than or equal to the second voltage PV2 and lower than a third voltage PV3. The threshold voltages of memory cells in a third program state C may be higher than or equal to the third voltage PV3. According to this example, in the erase state ERA and the first to third program states A, B, and C, data having different values may be stored in the memory cells.
According to this example, the first to third voltages PV1 to PV3 may be used to determine whether the memory cells have one of the erase state ERA and the first to third program states A, B, and C. In other words, the first to third voltages PV1 to PV3 may be used to verify whether memory cells have been properly programmed or to read data stored in memory cells.
A conventional verification operation is described in more detail below. When a memory cell is programmed, a program pulse is applied to a word line corresponding to the memory cell to be programmed. Thereafter, whether the memory cell has been programmed is verified by applying verification voltages to the word line corresponding to the memory cell to be programmed. The first to third voltages PV1 to PV3 are used as the verification voltages. After the verification operation, when it is determined that the memory cell has not been properly programmed, a program pulse is once again applied to the memory cell. After a verification operation, when it is determined that the memory cell has been properly programmed, the program operation of the memory cell is terminated.
As described above, the MLC may have a plurality of distributions of threshold voltages. Accordingly, in order to secure an adequate read margin when a read operation is performed on each of the types of states ERA, A, B, and C, the width of the threshold voltage distributions for each of the states ERA, A, B, and C needs to be narrow. A conventional method of narrowing the width of a threshold voltage distribution is described below with reference to FIG. 2.
FIG. 2 is a diagram illustrating a conventional method for narrowing the width of threshold voltage distributions. In the example of FIG. 2 memory cells are programmed in the first program state A of FIG. 1.
In a program operation, verification of whether memory cells have been programmed in the first program state A is performed using only the first voltage PV1 as a verification voltage. For narrowing the width of the threshold voltage distributions of the memory cells, however, the threshold voltages of the memory cells are verified once more using a first sub-voltage DPV1 which is lower than the first voltage PV1 as a sub-verification voltage.
According to this example, the selected memory cells are divided into first to third states. The first state is a non-program state in which the voltage levels of threshold voltages are lower than the first sub-voltage DPV1. The second state is a sub-program state in which the voltage levels of threshold voltages are higher than or equal to the first sub-voltage DPV1, and lower than the first voltage PV1. The third state is a program state in which the voltage levels of threshold voltages are higher than or equal to the first voltage PV1.
A bit line coupled to the selected memory cell is precharged to have a specific voltage depending on the state of the selected memory cell and whether the selected memory cell is a program target cell. A bit line coupled to a memory cell which is a program target cell in a non-program state is precharged with a ground voltage GND. A bit line coupled to a memory cell which is a program target cell in a sub-program state is precharged with a middle voltage Vm. A bit line coupled to a memory cell which is a program target cell in a program state, or which is not a program target cell is precharged with a core voltage Vcore.
A normal program operation is performed on memory cells coupled to a bit line precharged with the ground voltage GND when a program pulse is applied. A slow program operation is performed on memory cells coupled to a bit line precharged with the middle voltage Vm when a program pulse is applied. Memory cells coupled to a bit line precharged with the core voltage Vcore are not programmed although a program pulse is applied. That is, a program inhibition operation is performed on the memory cells coupled to the bit line precharged with the core voltage Vcore when the program pulse is applied.
During a normal program operation, the threshold voltage of a memory cell has relatively higher variation. During the slow program operation, the threshold voltage of a memory cell has relatively smaller variation. During the program inhibition operation, the threshold voltage of a memory cell is not changed. Hence, according to this conventional operation, a precharge time may be increased because a bit line needs to be precharged with one of the different three levels.